Technology Overview
Tilera™ has solved the multi-processor scalability problem with a revolutionary new chip architecture and programming tools set that can harness the processing power of hundreds of cores on a single chip. Tilera's technology addresses the biggest challenge in today's semiconductor market: offering a chip that is both high performance and easy to program.
New Architecture
Tilera's revolutionary architecture provides superior performance because it eliminates the on-chip bus interconnect, a kind of centralized intersection that information must flow through between cores within the chip, or before it leaves the chip. As manufacturers have added more cores to chips, the bus has created an information traffic jam because data from these additional cores must all still travel through a single bus.
Tilera's architecture eliminates the dependence on a bus, and instead puts a switch on each processor core, which connects it to a two dimensional on-chip mesh network called iMesh (Intelligent Mesh) This combination of the switch and a processor is called a "tile." The iMesh provides each tile with more than a terabit of bandwidth, creating a more efficient distributed architecture and eliminating the on-chip data congestion.
Further, the distributed nature of iMesh architecture can be used in creating computing grids as large or as small as necessary, creating a "computing-by-the-yard" scalability.
Next-Generation Programming Tools
Tilera's Multicore Development Environment is a complete, standards-based multicore programming solution that lets developers take a step-by-step "gentle slope programming" approach to large-scale multicore programming. Developers can start with familiar tools that are solidly rooted in industry standards. As they learn more, new tools that Tilera developed for large-scale multicore programming will enable them to program, debug or profile tens or even hundreds of cores in parallel.
