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TILEPro36 Processor

The TILEPro36™ processor brings the power of multicore computing to the mid-range of the embedded systems market, including 1-5 Gbps intelligent networking appliances, video endpoint systems and wireless base stations & core network controllers. This revolutionary processor features 36 identical processor cores (tiles) interconnected with Tilera's iMesh™ on-chip network. Each tile is a complete full-featured processor, including integrated L1 & L2 cache and a non-blocking switch that connects the tile into the mesh. The TILEPro family incorporates Tilera's DDC™ technology (Dynamic Distributed Cache) that accelerates coherent cache performance by a factor of two compared with other multicores. As with all Tilera processors, each tile can independently run a full operating system, or multiple tiles taken together can run a multi-processing OS like SMP Linux.

TILEPro36The TILEPro36 processor saves board real estate and system cost by integrating a complete set of memory and I/O controllers, thus eliminating the need for an external northbridge or southbridge. It delivers scalable performance, power efficiency and low processing latency in an extremely compact footprint.

With a standard ANSI C and C++ programming environment, developers can leverage their existing software investment as well as utilize the vast body of open source code available. Tiles can be grouped into clusters to apply the appropriate amount of horsepower to each application. Since multiple operating system instances can be run on the TILEPro36 simultaneously, it can replace multiple CPU subsystems for both the data plane and control plane.

Applications

Advanced Networking: The TILEPro36 processor provides the Ethernet line interfaces as well as the entire data plane processing for intelligent network services such as:

  • Network Security Appliances
  • L4-7 deep packet inspection
  • Network Monitoring & Forensics
 

Digital Video: The TILEPro36 processor also excels at digital video processing, easily taking the place of multiple DSPs as well as the networking components for:

  • Professional Video Editing
  • "Prosumer" Video Encoders
  • Audio/Video Transcoding Platforms
  • Video Conferencing Endpoints

Wireless Infrastructure:  With its flexibility to handle both signal processing and network packet processing, the TILEPro36 processor addresses a range of wireless network applications, including:

  • Base Transceiver Station (BTS)
  • Base Station Controllers (BSC)
  • Wireless backbone gateways (GGSN, SGSN, media gateway)
  

 

 

  Feature Enables

Massively Scalable Performance

  • 6 X 6 grid of identical, RISC processor cores (tiles) optimized for both signal processing and general purpose computing
  • 32-bit VLIW processors with 64-bit instruction bundle
  • 3.2 Mbytes of on-chip Cache
  • Up to 144 billion operations per second (BOPS)
  • 12 Tbps of on-chip mesh interconnect

  • 5 Gbps SNORT® processing
  • 5 Gbps iptables (firewall)
  • 8 Gbps nProbe
  • H.264 HD video encode: 3 streams of 1080p (videoconference quality)
  • 5 channels of OFDM baseband receiver processing (wireless)

Power Efficiency

  • 500MHz operating frequency
  • 9 – 13 Watts for typical applications
  • Idle Tiles can be put into low-power sleep mode
  • Power efficient inter tile communications

  • Highest performance per watt
  • Simple thermal management & power supply design
  • Small System form factor
  • Lower operating cost

Integrated Solution

  • Three 64-bit DDR2 memory controllers with optional ECC
  • 10Gbps Ethernet XAUI interface
  • 4-lane PCIe interface, Root complex or endpoint mode
  • Two GbE MAC interfaces
  • Flexible I/O interface

  • Reduces BOM cost – standard interfaces included on-chip
  • Dramatically reduced board real estate
  • Direct interface to leading L2-L3 switch vendors
  • High-speed I/O to peripherals such as HDD, USB, etc.

Ease of Programming

  • ANSI standard C / C++ compiler
  • Supports SMP Linux with 2.6 kernel
  • Accelerates pThreaded and shared-memory code
  • iLib™ API's for efficient inter-tile communication
  • Advanced profiling and debugging designed for multicore programming

  • Run off-the-shelf C and C++ programs
  • Leverage investment in existing code
  • Standard multicore communication mechanisms
  • Reduce debug and optimization time
  • Faster time to production code

 

TILEPro36

Product Briefs

Related Press

Testimonials

  • “By finding an efficient way to organize the flow of data to and from the chip's many cores, Tilera appeared to have overcome a fundamental design problem faced by the Next generation of high-capacity chips."
    Nathan Brookwood
    Insight64
    Read more