Tilera
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About Tilera

Tilera Corporation is a fabless semiconductor company and the industry leader in highly scalable multicore embedded processor design. Tilera's Tile processors are based on a new mesh architecture that scales to hundreds of full-featured cores on a single chip. The distributed nature of Tilera's revolutionary iMesh™ architecture provides an unprecedented combination of performance, power efficiency and programming flexibility.

Tilera products include a family of full-featured multicore processors that span a range of processing and power requirements, a complete set of standards-based multicore software development tools and a line of high performance boards.

Founded in October, 2004 and launched its first product, the 64-core TILE64™ processor in August 2007. Tilera is venture funded by Bessemer Venture Partners, Walden International, Columbia Capital and VentureTech Alliance. The company is headquartered in Santa Clara, Calif. and operates a research and development facility in Westborough, Massachusetts, USA.

Tile Processor™ History

The Tile Processor architecture is a significant step in the decades-long pursuit to harness the power of multiple processors and meet the performance requirements of executing compute intensive applications. The architecture has evolved to become the first design incorporating large numbers of full featured general purpose programmable processors on a single chip.

Early efforts by computer scientists relied on backplane or cluster technologies to connect multiple processors. One such effort was the Alewife project at MIT, led by Tilera CTO, Dr. Anant Agarwal in 1990. The Alewife project resulted in the development of a scalable multi-processor system built out of large numbers of single chip processors. Alewife machines integrated both shared memory and user-level message passing for inter-node communications. The machines demonstrated a pioneering 128-node mesh based cache-coherent multiprocessor.

In 1995, Dr. Agarwal founded Virtual Machine Works (now part of Mentor Graphics), which solved logic emulation by combining 100's of FPGA's using a mesh interconnect and a patented 'virtual wires' compiler.

In 1997, Dr. Agarwal proposed a follow-on project using a mesh technology to connect multiple cores. The follow-on project, RAW, which commenced in 2000, and was supported by DARPA/NSF's funding of tens of millions, resulting in the world's first 16-processor multicore processor and proving the mesh and compiler technology. The 16 cores were connected in a 4x4 mesh and were integrated onto one piece of silicon. The Raw processor enabled the seamless scaling of processors by connecting them via a 2D interconnection fabric. Raw chips could be gluelessly connected to make larger fabrics of processors - up to 1024 cores. The Raw processor was able to manage inter-processor communication of very large as well as very small quantum of data with extremely low latency and high bandwidth.

Heritage Chart
Tilera: A Rich Heritage

By 2004, Dr. Agarwal had demonstrated the functionality of the RAW processor to both ISSCC and ISCA. Recognizing the commercial potential for the technology, Dr. Agarwal licensed the technology from MIT, founded Tilera Corporation, and began drawing on the talent of many members of the original RAW team to architect the next generation multicore processor.

In 2005 and after securing first round of funding, Tilera pulled in top talent from industry leading companies to start developing the TILE64 processor and the Multicore Development Environment. The execution-oriented team developed silicon and software, and shipped first release in 2007 delivering the industry's highest performance embedded processor and an unmatched development environment.