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Tilera® has solved the multi-processor scalability problem with a revolutionary new chip architecture and a programming tool set that can harness the processing power of hundreds of cores on a single chip. Tilera's technology addresses the three biggest challenges in today's semiconductor market: offering a processor that is high performance, power-efficient, and easy to program.
Tilera's revolutionary architecture provides superior performance because it eliminates the on-chip bus interconnect, a centralized intersection that information must flow through between processor cores or between cores and the memory and I/O. As manufacturers have added more cores to chips, the bus (or ring) has created an information traffic jam because all data from these additional cores must travel through a single one-dimensional path.
Tilera's architecture eliminates the dependence on a bus, and instead puts a non-blocking, cut-through switch on each processor core, which connects it to a two dimensional on-chip mesh network called iMesh™ (Intelligent Mesh). This combination of the switch and a processor is called a 'tile'. The iMesh provides each tile with more than a terabit/sec of interconnect bandwidth, creating a more efficient distributed architecture and eliminating on-chip data congestion. Multiple parallel meshes are used in order to separate different transaction types and provide more deterministic interconnect throughput.
In order to achieve scalable multicore computing, a scalable caching system is required. Tilera's patent pending DDC™ (Dynamic Distributed Cache) technology provides a fully coherent shared cache system across an arbitrarily-sized array of tiles. Instead of using large centralized L2 or L3 caches that are power hungry and create system bottlenecks, Tilera's distributed cache is far more efficient. All of the L2 caches can be coherently shared among other tiles, evenly distributing the cache system load and presenting a very large, effective L3 cache.
Tilera has also incorporated the extremely efficient and innovative TileDirect™ system that moves I/O data directly into coherent cache without touching DDR memory. This significantly improves both latency and performance and lowers the load on external memory bandwidth.
Tilera’s Multicore Development Environment™ is a complete, standards-based multicore programming solution that lets developers enjoy rapid progress in scaling their application to large-scale multicore systems. Developers start with familiar tools that are solidly rooted in industry standards such as GCC, Eclipse, gdb, and oprofile. Tilera has taken these tools to new levels, however, and made them multicore-aware so that the developer can easily debug, profile, and optimize code running across dozens or even 100 cores.